Digital communications occur between sending and receiving devices over an intermediate communications medium, or “channel” (e.g., a fiber optic cable or insulated copper wires). Each sending device typically transmits symbols at a fixed symbol rate, while each receiving device detects a (potentially corrupted) sequence of symbols and attempts to reconstruct the transmitted data. A “symbol” is a state or significant condition of the channel that persists for a fixed period of time, called a “symbol interval.” A symbol may be, for example, an electrical voltage or current level, an optical power level, a phase value, or a particular frequency or wavelength. A change from one channel state to another is called a symbol transition. Each symbol may represent (i.e., encode) one or more binary bits of the data. Alternatively, the data may be represented by symbol transitions, or by sequences of two or more symbols.
Many digital communication links use only one bit per symbol; a binary ‘0’ is represented by one symbol (e.g., an electrical voltage or current signal within a first range), and binary ‘1’ by another symbol (e.g., an electrical voltage or current signal within a second range), but higher-order signal constellations are known and frequently used. In 4-level pulse amplitude modulation (PAM4), each symbol interval may carry any one of four symbols, typically denoted as −3, −1, +1, and +3. Two binary bits can thus be represented by each symbol.
Channel non-idealities produce dispersion which may cause each symbol to perturb its neighboring symbols, causing intersymbol interference (ISI). ISI can make it difficult for the receiving device to determine which symbols were sent in each interval, particularly when such ISI is combined with additive noise.
To combat noise and ISI, receiving devices may employ various equalization techniques including, for example, linear equalization and decision feedback equalization, either of which can take on different implementation structures that can operate in the continuous time domain, the digital domain, or a combination thereof. Each option presents certain potential advantages and disadvantages. For example, decision feedback equalizer may be desired for their ability to combat ISI without inherent noise amplification, but their feedback path becomes very challenging to implement at high data rates. As another example, digital domain equalization may be desired for its flexibility, but it requires analog-to-digital conversion beforehand with a commensurate power consumption demand that becomes prohibitive at high data rates.
One of the available equalization techniques is feed-forward equalization (FFE), a form of linear equalization employing a delay line with evenly spaced taps to implement a finite impulse response (FIR) filter. The filter is traditionally designed to minimize ISI and/or mean-square error between the equalized signal and the ideal (ISI and noise-free) transmit signal, subject to constraints existing on the number and resolution of the filter coefficients. In the high-data rate applications, the FFE implementation has been proposed in three forms: digital domain, analog sample-and-hold, and LC-based delay line. As previously mentioned, digital domain equalization (including FFE) imposes undesirably high power consumption requirements to digitize the receive signal with the necessary resolution at rates exceeding 10 GHz.
Analog sample and hold implementations, such as those proposed by Ankur Agrawal, et al., “A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS”, IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 3220-3231, December 2012; and J. E. Jaussi et al., “8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew,” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 80-88, January 2005; appear to provide accurate line delays, but at the needed data rates they also impose undesirably high power requirements for clock distribution, sampling switches, and buffers. Moreover, sample-and-hold implementations do not (without additional mechanisms such as oversampling) enable the use of the popular Alexander or Mueller-Muller techniques for recovering the clock from the data.
LC-based delay lines, such as that proposed by A. Momtaz and M. M. Green, “An 80 mW 40 Gb/s 7-tap T/2-spaced feed-forward equalizer in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 629-639, March 2010, consume large chip areas and require re-design whenever the tap delays must be adjusted. Thus the available FFE implementations are unsatisfactory.